1. Field of the Invention
This invention relates to boundary scan testing. More particularly, this invention relates to a post-mission test method for assuring the integrity of the boundary scan test.
2. Background Art
Boundary scan is a testing standard formally known as IEEE/ANSI Standard 1149.1-1990. Boundary scan is applied principally at the Integrated Circuit (IC) level. Boundary scan ICs are designed with shift registers or cells place between each device pin and the internal logic of the IC. These cells allow an operator to control and observe what happens at each input and output pin. When these cells are connected together they form a data register chain, called the Boundary Register, defining a scan path. Additional registers within a boundary scan IC include and Instruction Register, which decodes instruction bits that allow the IC to perform various functions; a Bypass Register, which provides a one-bit scan path that minimizes the distance between the scan input and the scan output; an Identification Register, called the IDCODE Register, which identifies the device and manufacturer; and other designer-specified data registers, which typically perform internal test functions.
Boundary scan ICs are designed to be linked together into chains. A simple chain includes boundary scan ICs with common test clock terminals (TCK) and test mode select terminals (TMS); and with the scan paths of the ICs linked together by connecting a test data out (TDO) terminal of one IC to the test data in (TDI) terminal of the following IC.
For purposes of the following discussion, testing with boundary scan principles and techniques, and boundary scan IC chips and scan paths is referred to as boundary scan testing. A mission test includes a complete single test, such as an interconnect test, a connection test or an interaction test, as well, IC internal logic tests. A test frame refers to a portion of a mission test involving shifting in a test vector, writing the test vector to the test logic, which is part of the testing infrastructure, capturing a test result and shifting out the test results.
A more detailed discussion of boundary scan testing is provided in IEEE Standard 1149.1-1990, "IEEE Standard Test Access Port and Boundary Scan Architecture," IEEE Standards Board; "HP Boundary Scan Tutorial and BSDL Reference Guide," Hewlett-Packard Company, HP Part Number E1017-90001, 1990; and Kenneth P. Parker, The Boundary-Scan Handbook, (Kluwer Academic Publishers, 1992); each of which is incorporated herein by reference.
Prior to executing useful mission testing, an operator has to be able to depend upon the chain of register cells being in operational order. Therefore, the basic function of the chain needs to be assured before the results of the mission test can be relied upon. Testing the integrity of the chain prior to executing boundary scan testing is discussed in detail in The Boundary-Scan Handbook at pp. 114-117.
However, it has been identified by the inventors that it is possible that during execution of a mission test, an operational flaw in the scan path may occur, causing the integrity of the scan path to be compromised. For example, a test induced ground bounce or a timing condition may cause the integrity of the mission test to be compromised after the pre-mission test integrity test has been performed and, more particularly, during mission test execution.
If this occurs, the mission test results will be inaccurate. Diagnosing the inaccurate test results will result in invalid or erroneous diagnostic information. If this diagnostic information is relied upon, a significant amount of a technician's time may be wasted in attempting to repair faults that, in reality, do not exist. What it is needed is a method to detect when such an operational flaw occurs so that invalid test results can be discarded.